This listing was posted on ITJobsWeb.
Senior IP Design and Reliability Engineer
Location:
Hillsboro, OR
Description:
Job Description Join Intel and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us and help us create the next generation of technologies that will shape the future for decades to come. To support Intel IDM2.0 and Foundry strategy, we are looking for talents to join this exciting journey to drive design enablement with focus on quality and reliability area to build industry competitive design platform supporting both internal design and external designs on Intel leading edge technologies. The general reliability design enablement includes pathfinding and development in PDK (Process Design Kits), TFM (tool/flow/methodology, IP (library, memory, analog IP) and DFR (Design for Reliability) to achieve best PPA (Power Performance Area) and reliability co-optimization. This role will be responsible for but not limited to of the following areas: - Lead and define industry competitive reliability spec, methods and DFR methodology for IP and SOC design enabling Intel foundry design platform supporting both internal and external customers. - Working with internal and external Foundational IP (FIP), analog and mixed signal IP design to define requirement, review and sign off design collateral and IP to meet reliability requirement for various market segments, coordinate and program manage IP development life cycle including Pre-Si verification, test chip intercept and Post-Si validation to ensure design quality and reliability. Competitive benchmarking, DTCO/STCO (Design/System Technology Co-Optimization) for technology definition and design enablement in reliability domain, enable and deliver industry leading PDK, design rule, design collateral, FIP and complex IP to enable internal and external customer design on Intel technology. - Drive EDA tool and flow enablement and align with IP and EDA vendors to deliver competitive IP and TFM with Ease of Use (EoU) features to delight our customers. The Candidate Should Exhibit the Following Behavioral Traits: - Written and verbal communication and presentation skills. - Demonstrated experience working with and or managing teams using and converting technical data into presentations. - Passion for quality and attention for details and procedures. - Demonstrated capability to drive quality enhancements projects. - Team player with proven ability to work in diverse multi-cultural environment. - Ability to work effectively within a global team spanning multiple countries and cultures. - Leadership capabilities building, motivating, coaching, and directing cross-functional teams and team members to meet project objectives. - Must be flexible and adaptable to ensure program commitments are met on time in a dynamic work environment. #DesignEnablement Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate must possess a BS degree with 4+ years of experience or MS degree with 3 + years of experience or PhD degree with 1 + years of experience in E lectrical E ngineering, P hysics or related field. Experience in one of the following areas: Design for reliability , reliability tool and flow development , foundational IP , hard IP , test chip design and post-Si validation. Preferred Qualifications: Experience in the following: - Industry experience on IP design and validation process with Foundry or Fabless design or 3rd party IP design house, familiar with design and reliability validation methods and requirements. - Experience on hard IP design or foundational IP design and project management from Pre Si reliability to Post Si test chip validation such as HTOL, ELT etc; understanding JEDEC standard and general design expectation between Foundry and fabless design company. - Experience on standard cell design, memory compiler, ESD clamp, diode design, foundational or advanced analog, mixed-signal IP design, and reliability verification at IP and SOC level. - Experience and knowledge on reliability verification and physics such as aging including BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection), Electro-Migration, high voltage design, EOS (Electrical Over-Stress), ESD (Electrostatic Discharge), etc. - Experience on PDK, EDA tool/flow/methodology and their application in IP and SOC design, familiar with design flow and EDA (Electronic Design Automation) tools for reliability simulation and validation in one or multiple areas. Inside this Business Group As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth. Other Locations US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00*Salary range dependent on a number of factors including location and experience Working Model This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs. Requisition #: JR0261854pca3lyuhf
Company:
Intel
Posted:
April 13 on ITJobsWeb
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More About this Listing: Senior IP Design and Reliability Engineer
Senior IP Design and Reliability Engineer is a Engineering Engineer Job at Intel located in Hillsboro OR. Find other listings like Senior IP Design and Reliability Engineer by searching Oodle for Engineering Engineer Jobs.
Senior IP Design and Reliability Engineer is a Engineering Engineer Job at Intel located in Hillsboro OR. Find other listings like Senior IP Design and Reliability Engineer by searching Oodle for Engineering Engineer Jobs.